The integration density and storage capacity of nonvolatile memory devices have been increased by decreasing the size of active regions and isolation films within cell array regions of the devices. One approach for fabricating such devices uses a self-aligned polysilicon fabrication process. The circuit area of a memory device may be reduced using the self-aligned polysilicon fabrication process by forming a floating gate pattern on an area that is confined between adjacent device isolation films.
U.S. Pat. No. 6,656,793, entitled “Method of forming a self aligned floating gate in flash memory cell”, discloses a process for enlarging a surface area of a floating gate pattern through a self-aligned polysilicon fabrication process. After forming the floating gate pattern on a region that is defined between adjacent device isolation film, the device isolation film is partially removed through an isotropic etching process to expose sidewalls of the floating gate pattern.
FIG. 1 is a cross sectional view of a conventional nonvolatile memory device. Referring to FIG. 1, a semiconductor substrate 50 is grooved to form trenches with active regions 59 therebetween, and a device isolation film 58 is formed in the trenches. A tunnel insulation film (60 in FIGS. 3 and 4) is formed on the active regions 59 of the substrate 50. Floating gates 62 are formed on the tunnel insulation film (60 in FIGS. 3 and 4) over the active regions 59 of the substrate 50.
An inter-gate dielectric film 64 is formed on the floating gates 62 and the device isolation film. A control gate pattern 66 is deposited on the inter-gate dielectric film 64 over the floating gates 62. An upper surface of the device isolation film 58 is lower than an upper surface of the floating gates 62, and the interlevel dielectric film 64 covers a portion of sidewalls of the floating gates 62. The floating gates 62 are wider than the substrate 50 between the trenches, so that they partially overlap the trenches. Forming the control gate pattern 66 on sidewalls of the floating gates 62 and overlapping the floating gates 62 with a portion of the trenches can increase the capacitive coupling between the control gate pattern 66 and the floating gates 62.
FIGS. 2, 3, and 4 are cross sectional views of conventional nonvolatile memory devices and illustrate methods of fabricating the same.
Referring to FIG. 2, the substrate 50 is etched to form the plurality of trenches. The device isolation film 58 is deposited to fill the trenches. After its deposition, the device isolation film 58 includes projections that extend away from the substrate 50.
Referring to FIG. 3, the device isolation film 58 is recessed by an isotropic etching process so that its upper surface is below an upper surface of the substrate 50, leaving the tunnel insulation film 60 between the floating gates 62 and the substrate 50. Each of the floating gates 62 is wider than the width of the active region 59 of the substrate 50 between the trenches. The isotropic etching of the device isolation films 58 at least partially exposes sidewalls of the floating gates 62.
When the sidewalls of the floating gates 62 are completely exposed by etching of the device isolation film 58, the tunnel insulation film 60 between the floating gates 62 and the substrate 50 may be partially removed. Such partial removal of the tunnel insulation film 60 may degrade the uniformity of the operational characteristics of a cell array in the memory device that includes such structures. Partial removal of the tunnel insulation film 60 may be avoided by only partially exposing the sidewalls of the floating gates 62 when etching the device isolation film 58. However, only partially exposing the sidewalls of the floating gates 62 may not provide an adequate capacitive coupling between the floating gates 62 and a subsequently formed control gate pattern 66.
Referring to FIG. 4, the inter-gate dielectric film 64 is conformably formed over the entire exposed upper surface of the structure of FIG. 3. The control gate film 66 is deposited on the inter-gate dielectric film 64. As shown in FIG. 4, opposite edge portions of a lower surface of the floating gates 62 are directly on the inter-gate dielectric film 64, and the control gate film 66 extends within an undercut region 70 below the opposite edge portions of the floating gates 62. The control gate film 66 within the undercut region 70 may form an undesirable conductive bridge between some of the floating gates 62.